The voltage used to drive large scale integrated circuits has been reduced in recent years, and the threshold voltages (Vt or Vth) of transistors have been lowered. Lowering threshold voltages increases sub-threshold leakage current. Leakage current may flow during an active period when a circuit is in operation and also flow during a standby period. A high speed logic circuit may have low threshold voltages but high leakage currents. There is a tradeoff between threshold voltage and leakage current.
Reducing leakage current during standby in devices such as cell phones, lap tops or personal digital assistants (PDAs) may increase the life of the devices batteries. There may be a desire for developing circuits with minimum possible leakage current.
So-called “Dual-Vth” technology has been developed to reduce leakage current. Circuit designers may use computer-aided design (CAD) systems to design dual-Vth circuits with both low threshold voltage cells (formed with low threshold voltage transistors) and high threshold voltage cells (formed with high threshold voltage transistors). Leakage current may be reduced by using high threshold voltage cells with low speed operation on a path with less critical timing needs. A path with more critical timing needs may use low threshold voltage cells with high speed operation. These paths have increased leakage current as a tradeoff for their increased speed.